In a system having multiple electronic devices, such as an electronic system including many devices assembled on a printed circuit board, it is necessary to select the manner in which communication is to be performed between the devices. In general, there are two techniques of communication: serial or parallel. In one type of serial communication system all devices are coupled to a serial data (SDA) line and a serial clock (SCL) line. Each of the SDA and SCL are single bit lines, hence data is transferred one bit at a time (i.e. serially) on the SDA at a rate determined by the clock being transmitted on the SCL line.
In one such prior art serial communication system (developed by Philips Semiconductor), the SDA and SCL lines are referred to as the I.sup.2 C bus. The I.sup.2 C bus has an associated set of rules, or protocol, that characterize how communication and arbitration between devices is performed on the I.sup.2 C bus. The protocol of the I.sup.2 C bus eliminates or reduces the possibility of confusion of data transfer origin/destination, of information blockage, or data loss. For instance, if two devices initiate data transfers, the I.sup.2 C protocol determines which device is able to perform the data transfer depending on the particular SDA and SCL line conditions that have occurred or are occurring. Furthermore, in this type of system, only one device at a time (referred to as the master) can control the transfer of information on the SDA and SCL lines to any other device (referred to as a slave) coupled to the SDA and SCL lines. The master device provides the clock signal on the SCL line and data is transferred on the SDA line from the master device to the slave device, or vice versa.
One manner in which the I.sup.2 C bus protocol is implemented is by defining the conditions on the SDA and SCL lines that indicate the start and stop of a data transfer operation. Detection and identification of the start and stop conditions alerts the devices coupled to the I.sup.2 C bus as to whether they can or cannot initiate a data transfer on the SDA. The start and stop conditions must be unique conditions occurring only when the particular designated event occurs (i.e. start or stop of transmission).
It is typical in prior art serial data transfer systems to employ a slave controller which generally resides within each slave device. The slave controller communicates with the master device when performing data transfers on the SDA line. For instance slave controllers often identify the start and stop of data transmissions, which slave device is being accessed or transmitted to, acknowledgment signals, and other conditions relating to the transfer of data.
The slave controller requires detection circuitry to identify the start and stop conditions of data transfers on the SDA and SCL lines so it can perform its many functions. Currently, the detection of the start and stop conditions within a slave controller (and in other slave devices) is performed by a first stage that samples the SDA and SCL lines and an interpretation stage that interprets the sampled states provided by the first stage. The first stage samples the lines at a high frequency clock rate (typically greater than 1.0 MHz) which is greater than the clock rate of the SCL line which typically transitions at a rate of up to 100 kHz. The sample circuitry generally includes two flip-flop devices each one having its data input coupled to one of the SDA and SCL lines and its clock input coupled to the high frequency sampling clock signal. The sampling clock signal can be generated internal to the slave controller, on a separate clock chip, or may be provided by some other external source. The output of each flip-flop is the logic state sampled on the SDA and SCL lines. The sample circuit provides the sampled states (or conditions) of the SDA and SCL lines to the interpretation stage which interprets these states and determines whether a start or stop condition has occurred.
The start and stop conditions on an I.sup.2 C bus are defined as follows: 1) a start condition occurs when the SDA line is transitioning high-to-low while the SCL line is high, 2) a stop condition occurs when the SDA line is transitioning low-to-high while the clock is in a high state. Hence, when the prior art sample flip-flop coupled to the SDA line outputs a low state and the sample flip-flop coupled to the SCL line outputs a high state during the same sample clock phase and these output states are coupled to the interpretation stage, a start condition is detected by the interpretation logic. Furthermore, when the flip-flop sampling the SDA line outputs a high state and the flip-flop sampling the SCL line outputs a high state during the same sample clock phase and these output states are coupled to the interpretation stage, a stop condition is detected. Typically, the interpretation logic is clocked by the sampling clock signal so as to be synchronized with the sampling circuitry.
There are several drawbacks to the prior art slave controller detection system. First, it requires the additional sample clock signal which is generated either external or internal to the slave controller. This additional high frequency clock presents several disadvantages within the prior art slave controller such as added noise, additional integrated circuit or printed circuit board space, and added power dissipation to generate the sample clock signal. Secondly, the sampling flip-flops are constantly sampling the SDA and SCL lines and hence, are constantly dissipating power. Third, this type of detection circuitry requires two stages: the flip-flop stage to sample the SDA and SCL lines and an interpretation stage to interpret the states of the sampled SDA and SCL lines. Hence, additional circuit space is consumed by the interpretation logic. Furthermore, since the interpretation logic stage is typically synchronized with the sample clock, additional circuit space is consumed by the interconnection of the sample clock signal to the interpretation logic. Finally, it is often common practice to implement each individual flip-flop in the sampling stage of the prior art slave controller detection system with multiple series connected flip-flops. Specifically, instead of using two flip-flops to sample the SDA and SCL lines, four flip-flops are employed. The four flip-flop sample stage is implemented in the following manner: the first flip-flop has its input coupled to the SDA line and its output coupled to the input of the second flip-flop. The output of the second flip-flop is the sampled state of the SDA signal. Similarly, the third flip-flop has its input coupled to the SCL line and its output coupled to the input of the fourth flip-flop. The output of the fourth flip-flop is the sampled state of the SCL signal. Each of the first through fourth flip-flops are clocked by the sample clock signal. This multiple flip-flop implementation takes into account slow transitioning signals on the SDA and SCL lines that may result in the false interpretation of start or stop conditions. However, this implementation consumes even more space and power within the slave controller than the two flip-flop sample stage implementation.
Another aspect of a master/slave serial communication system is that the master device often interfaces with multiple slave devices having different serial communication protocols. For instance, one type of serial communication device uses a serial communication protocol referred to as SPI (developed by Motorola). The SPI protocol uses four bi-directional pins: MISO (Master In/Slave Out), MOSI (Master Out/Slave In), SCK (Serial Clock), SS (Slave Select). Furthermore, data is clocked out of the SPI slave device with the falling edge and clocked into the slave device with the rising edge of the SCK. SPI serial communication defines a hardware interface (i.e. the four bi-directional pins) and partially, a software protocol. Another type of serial communication interface is referred to as MicroWIRE (developed by National Semiconductor). The MicroWIRE interface differs from SPI in that it does not specifically define any protocol. Instead, it only defines a basic set of signal lines to interconnect two or more devices. A MicroWIRE interface has four signal lines: CS (Chip Select), SK (Serial clock), DI (Data In), DO (Data Out). These are analogous to SS, SCK, MISO, and MOSI of the SPI interface. The main difference between the physical portion of the MicroWIRE and SPI interfaces is that a MicroWIRE slave device clocks both input and output data on the rising edge only and the falling edge has no effect on the devices. This means a MicroWIRE device must be read differently than a SPI compatible device due to the different clocking requirements.
As a result of the differing protocol and interconnection characteristics of the various serial communication slave devices, an I.sup.2 C master device is often designed with multiple ports for interconnecting between each of these varying protocol type slave devices. Specifically, an I.sup.2 C master device is often designed to include SDA and SCL ports for interfacing with other I.sup.2 C slave devices in addition to separate serial input, output, clock, and chip select ports for interfacing with the other protocol type slave devices such as SPI or MicroWIRE devices (i.e. a total of six interconnection ports). Furthermore, it is often common to implement a communication system in which the master and slave devices reside on separate printed circuit boards (PCBs) thus requiring multiple physical interconnections between the boards. In other words, in the above case, a total of six physical interconnects would be required in order to couple the master device on a first PCB with the slave devices on a second PCB to accommodate the different types of serial communication slave device protocols. These physical interconnections between the PCBs represent a potentially large amount of undesirable EMI in a communication system.
What is needed is a more space and power efficient implementation of a SDA and SCL state detector in a slave controller and thus an overall reduced power and smaller slave controller. In addition, what is needed is a manner in which to implement a multiple board serial communication system having slave devices using more than one serial communication protocol which is other than the master device protocol.